Power-Constrained Testing of VLSI Circuits J. Koerting Virtuelle Kommune Netz: Das Leben

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Power-Constrained Testing of VLSI Circuits J. Koerting Virtuelle Kommune Netz: Das LebenThis text focuses on techniques for minimizing power dissipation during test application at logic and register transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan based sequential circuits and BIST data paths. A Guide to the IEEE 1149. 4 Test Standard A Guide to the IEEE 1149. 4 Test Standard